1. Field of the Invention
The present invention relates to a semiconductor IC and, more particularly, to a semiconductor IC including an input circuit in which a low threshold voltage is set.
2. Description of the Related Art
Generally, in a semiconductor IC, two standards of a TTL level and a CMOS level are often used as references of a signal level. In these standards, low level voltage V.sub.IL and high level voltage V.sub.IH to be satisfied by a pulse signal are defined as follows.
______________________________________ V.sub.IL V.sub.IH ______________________________________ TTL level 0.8 V 2.0 V CMOS level V.sub.DD .times. 0.3 V.sub.DD .times. 0.7 ______________________________________
In the above Table, V.sub.DD is a power source voltage. For example, assuming that V.sub.DD =5V, V.sub.IL and V.sub.IH at the CMOS level are 1.5 V and 3.5 V, respectively. That is, at the TTL level, a low level voltage (pulse base amplitude) of a pulse signal must be 0.8 V or less, and its high level voltage (pulse top amplitude) must be 2.0 V or more. At the CMOS level, when a power source voltage is 5 V, the low level voltage of a pulse signal must be 1.5 V or less, and its high level voltage must be 3.5 V or more. That is, a pulse signal of a TTL level has a lower DC level and a smaller amplitude than those of a pulse signal of a CMOS level. For this reason, a signal of a TTL level has a smaller noise margin than that of a signal of a CMOS level. Therefore, a logic circuit which receives a signal of a TTL level is more easily affected, in an adverse manner, by noise than a logic circuit which receives a signal of a CMOS level.
In a semiconductor IC having a CMOS arrangement, all signals transmitted inside a chip are at the CMOS level. However, an external input signal is not always at the CMOS level, but is often input at the TTL level. For this reason, a threshold voltage of an input circuit which receives an external input signal is set to be low so that logic "0" and "1" are correctly determined in accordance with a signal of a TTL level. Therefore, in a semiconductor IC having the CMOS arrangement, it is likely that an erroneous operation of an input circuit will occur. For this reason, in a semiconductor IC such as a memory of multi-bit output in which power source noise is easily generated, the problem of an input circuit erroneously operating in response to the power source noise, is posed.
Power source noise of a semiconductor IC is generated as a result of its circuit operation. For example, when "0" level outputs are output from all output buffers in a memory of multi-bits, a considerably large current instantaneously flows through a ground line because the ground line having a parasitic resistance and a parasitic inductance. As a result, a potential of the ground line varies around 0 V. Since a threshold voltage of an input circuit varies in accordance with a power source voltage, the threshold voltage of the input circuit is reduced when the potential of the ground line is reduced below 0 V. Therefore, even if an input voltage externally supplied to the input circuit satisfies logic "0", the threshold voltage of the input circuit may sometimes be lower than the input voltage. In this case, the input circuit erroneously operates as if an input voltage of logic "1" had been supplied thereto.